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| Main centres: | 1-3 business days |
| Regional areas: | 3-4 business days |
| Remote areas: | 3-5 business days |
| Microarchitecture | Sandy Bridge |
| Processor core | Sandy Bridge-E |
| Core steppings | C1 (SR0H9) C2 (SR0KY) |
| Manufacturing process | 0.032 micron Hi-K metal gate process |
| Data width | 64 bit |
| Number of cores | 6 |
| Floating Point Unit | Integrated |
| Level 1 cache size | 6 x 32 KB instruction caches 6 x 32 KB data caches |
| Level 2 cache size | 6 x 256 KB |
| Level 3 cache size | 12 MB |
| Physical memory (GB) | 32 |
| Multiprocessing | Uniprocessor |
| Features |
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| Low power features | Enhanced SpeedStep technology |
| On-chip peripherals |
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| ¿ | |
| Electrical/Thermal parameters | |
| Maximum operating temperature (¿C) | 72.6 |
| Thermal Design Power (W) | 130 |
