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Divide-By-N Counter Counter, 8.5 MHz, 3 V to 18 V, DIP-16Product OverviewThe CD4018BE is a CMOS Pre-settable divide-by-N Counter consists of 5Johnson-counter stages, buffered Q outputs from each stage and counter pre-setcontrol gating. CLOCK, RESET, DATA, PRESET ENABLE and 5 individual JAM inputsare provided. Divide by 10, 8, 6, 4 or 2 counter configurations can beimplemented by feeding the Q\5, Q\4, Q\3, Q\2, Q\1 signals respectively, back tothe DATA input. Divide-by functions greater than 10 can be achieved by use ofmultiple CD4018B units. The counter is advanced one count at the positiveclock-signal transition. Schmitt Trigger action on the clock line permitsunlimited clock rise and fall times. A high RESET signal clears the counter toan all-zero condition. A high PRESET-ENABLE signal allows information on the JAMinputs to pre-set the counter. Anti-lock gating is provided to assure the propercounting sequence.Fully static operation100% Tested for quiescent current at 20VStandardized, symmetrical output characteristicsMeets all requirements of JEDEC tentative standard #13BApplicationsClock & Timing, IndustrialProduct InformationLogic Family / Base Number: CD4018Counter Type: PresettableClock Frequency: 8.5MHzCount Maximum: 31Logic Case Style: DIPNo. of Pins: 16PinsSupply Voltage Min: 3VSupply Voltage Max: 18VLogic IC Family: CD4000Logic IC Base Number: 4018Operating Temperature Min: -55°COperating Temperature Max: 125°CProduct Range: CD4000 LOGICMSL: -