Texas Instruments (SN65LVDS94DGG) SerDes, Serialiser / Deserialiser

Product OverviewThe SN65LVDS94DGG is a LVDS SerDes (Serializer/Deserializer) Receiver containsfour serial-in 7-bit parallel-out shift registers, a 7 x clock synthesizer andfive low-voltage differential signalling (LVDS) line receivers in a singleintegrated circuit. These functions allow receipt of synchronous data from acompatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over fivebalanced-pair conductors and expansion to 28 bits of single-ended LVTTLsynchronous data at a lower transfer rate. When receiving, the high-speed LVDSdata is received and loaded into registers at the rate seven times the LVDSinput clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallelbus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a7 x clock for internal clocking and an output clock for the expanded data. TheSN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).4:28 Data channel expansion at up to 1.904 gigabits per second throughputSuited for point-to-point subsystem communication with very low EMIRising clock edge triggered outputsBus pins tolerate 4kV HBM ESDNo external components required for PLLOperates from a single 3.3V supply and 250mW (typical)Consumes